// IVB checksum: 1471781567
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File name   :  vv_ahblite_smp_h.e
Title       :  Signal map declaration
Project     :  vv_ahblite UVC
Developers  :  stefan,filip
Created     :  26.07.2011.
Description :  This file declares the signal map of the UVC.

Notes       :  The signal map is a unit that contains external ports
            :  for each of the HW signals that the agent must access 
            :  as it interacts with the DUT.
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Copyright  (c)2011
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<'
package vv_ahblite;

--=========================================================================
-- General bus signal map. Contains the names of the general bus signals
--=========================================================================
unit vv_ahblite_smp {
    
    -- This field is the logical name of the env associated with this
    -- signal map. This field is automatically constrained by the UVC. Do
    -- not constrain it manually.
    env_name   : vv_ahblite_env_name_t;
    
    -- enables the default slave      
    has_default_slave :bool;
    keep  soft has_default_slave == TRUE; 
    ----- 
    -- The default slave hsel signal
    AHB_DEFAULT_SLAVE_HSEL: inout simple_port of bit;
    -- Default slave transfer done (out)
    AHB_HREADY: inout simple_port of bit ;
    -- Default slave transfer response (out)
    AHB_HRESP: inout simple_port of bit ;
    --Default slave hrdata
    AHB_HRDATA: inout simple_port of vv_ahblite_data_t ;
    
    
    
-- Request Content

    h_addr   : inout simple_port of vv_ahblite_addr_t is instance;

    h_write  : inout simple_port of bit is instance;
    
    h_size   : inout simple_port of uint(bits : 3) is instance;

    h_burst  : inout simple_port of uint(bits : 3) is instance; 

    h_prot   : inout simple_port of uint(bits : 4) is instance;

    h_trans  : inout simple_port of uint(bits : 2) is instance;

    h_mastlock : inout simple_port of bit is instance;

    h_wdata : inout simple_port of vv_ahblite_data_t is instance;
    -------------------------------------------------------------

    -- MULTIPLEXER OUTPUTS
    h_ready : inout simple_port of bit is instance;
    h_resp  : inout simple_port of bit is instance;
    h_rdata : inout simple_port of vv_ahblite_data_t  is instance;
    ----------------------------------------------------------------
    
    -- HSELi SIGNALS
    h_sel_s0	: inout simple_port of bit is instance;
    h_sel_s1	: inout simple_port of bit is instance;
    h_sel_s2	: inout simple_port of bit is instance;
    h_sel_s3	: inout simple_port of bit is instance;
    ----------------------------------------------------
    
    -- SLAVE OUTPUTS HRDATA, HRESP, HREADYOUT
    h_rdata_S0 : inout simple_port of vv_ahblite_data_t  is instance;
    h_resp_S0  : inout simple_port of bit is instance;
    h_readyout_S0  : inout simple_port of bit is instance;    
    
    h_rdata_S1 : inout simple_port of vv_ahblite_data_t  is instance;
    h_resp_S1  : inout simple_port of bit is instance;
    h_readyout_S1  : inout simple_port of bit is instance;
    
    h_rdata_S2 : inout simple_port of vv_ahblite_data_t  is instance;
    h_resp_S2  : inout simple_port of bit is instance;
    h_readyout_S2  : inout simple_port of bit is instance;
    
    h_rdata_S3 : inout simple_port of vv_ahblite_data_t  is instance;
    h_resp_S3  : inout simple_port of bit is instance;
    h_readyout_S3  : inout simple_port of bit is instance;
    --------------------------------------------------------

    -- This method samples the h_size signals and returns the
    -- appropriate enumerated value. It is assumed that this method
    -- will only be called when the use of these signals is valid. 
    package get_h_size() : vv_ahblite_data_size_t is {
        case h_size$ {
            0b000  : { result = BYTE; };
            0b001  : { result = HALFWORD; };
            0b010  : { result = WORD; };
            0b011  : { message(FULL, "An illegal h_size value was asserted.[DOUBLE WORD]"); 
                     result = WORD; };
            0b100  : { message(FULL, "An illegal h_size value was asserted.[4-WORD LINE]"); 
                     result = WORD; };
            0b101  : { message(FULL, "An illegal h_size value was asserted.[8-WORD LINE]"); 
                     result = WORD; };
            0b110  : { message(FULL, "An illegal h_size value was asserted.[16-WORD LINE]"); 
                     result = WORD; };
            0b111  : { message(FULL, "An illegal h_size value was asserted.[32-WORD LINE]"); 
                     result = WORD;  };
            };
    }; -- this method can be modified if larger data bus is being implemented


    -- This method gets the data size of a transaction in
    -- enumerated form and drives the bus read and write signals
    -- appropriately.
    package drive_h_size(hsize : vv_ahblite_data_size_t) is {
        case hsize {
            BYTE      : { h_size$ = 0b000; };
            HALFWORD  : { h_size$ = 0b001; };
            WORD      : { h_size$ = 0b010; };
            default   : { message(FULL, "An illegal h_size value was driven.Assuming word size"); h_size$ = 0b010;   };
        };
    };
    
    
     package get_h_burst() : vv_ahblite_burst_t is {
        case h_burst$ {
            0b000  : { result = SINGLE; };
            0b001  : { result = INCR; };
            0b010  : { result = WRAP4; };
            0b011  : { result = INCR4; };
            0b100  : { result = WRAP8; };
            0b101  : { result = INCR8; };
            0b110  : { result = WRAP16; };
            0b111  : { result = INCR16; };
            };
    };
    
    package drive_h_burst(hburst : vv_ahblite_burst_t) is {
        case hburst {
            SINGLE  : { h_burst$ = 0b000; };
            INCR  : { h_burst$ = 0b001; };
            WRAP4 : { h_burst$ = 0b010; };
            INCR4 : { h_burst$ = 0b011; };
            WRAP8 : { h_burst$ = 0b100; };
            INCR8 : { h_burst$ = 0b101; };
            WRAP16 : { h_burst$ = 0b110; };
            INCR16 : { h_burst$ = 0b111; };
            };
};

    package get_h_trans() : vv_ahblite_transfer_t is {
        case h_trans$ {
            0b00  : { result = IDLE; };
            0b01  : { result = BUSY; };
            0b10  : { result = NONSEQ; };
            0b11  : { result = SEQ; };
            };
    };

    package drive_h_trans(htrans : vv_ahblite_transfer_t) is {
        case htrans {
            IDLE   : { h_trans$ = 0b00; };
            BUSY   : { h_trans$ = 0b01; };
            NONSEQ : { h_trans$ = 0b10; };
            SEQ    : { h_trans$ = 0b11; };
        };
    };
    
    
    
    -- **********************************************************************
}; 

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